The invention relates generally to image processing and, more particularly, to the control of image sensor arrays.
The success of 2D sensor development has permitted relatively high levels of integration, so that several blocks, such as timing control, PGA and ADC can be provided together with a 2D sensor array (for example a CMOS array) on a single integrated circuit chip. A conventional example of such a single chip imager 10 is illustrated in the conventional system diagram of FIG. 1.
As the use of digital cameras, video conferencing and digital video has increased, a corresponding increase in the need for image compression has arisen. FIG. 1 illustrates conventional components of an imaging compression architecture, including an image processing chip 13 which includes a compression engine 14, and a suitable memory chip 15. A multi-chip architecture such as shown in FIG. 1 has several disadvantages, including the expense of the individual chips, the space requirements of the individual chips, and the total power consumption of the multi-chip architecture. These factors can vary with the size and complexity of the individual chips. For example, as the size and/or pixel resolution of the sensor array 12 within the imager 10 increases, the size of the memory chip 15 also increases.
Many conventional image compression algorithms process pixel elements in 8xc3x978 blocks. Using a Discrete Cosine Transform (DCT), wherein each 8xc3x978 block includes 8 row pixel elements and 8 column pixel elements. In conventional image processing arrangements, the image is read out in rows of pixels starting from the top (or bottom) of the sensor array and working down (or up). This requires the compression engine to store 8 complete rows of pixel data before it can actually begin compression operations. Moreover, because the image compression operations would, in general, be performed concurrently with the process of reading pixels from the sensor, the compression engine would normally read out the next 8 rows of pixel data while compressing blocks from the previous 8 rows. Thus, for real time compression in this example, the memory of FIG. 1 must be adequately sized to store 16 complete rows of pixels. Many conventionally available sensor arrays can include more than 3 million pixels, with over 2,000 pixels per row. Assuming a resolution of 8 bits/pixel, more than 16xc3x972000=32,000 bytes of memory would be needed to permit the compression engine to operate in real time.
FIG. 2 illustrates a conventional example of a 2D CMOS sensor array. In the pixel detail of FIG. 2, R_SW designates a row reset switch, and S_SW designates a row select switch. The row reset switches of the pixels of a single pixel row are connected together by metal lines, as are the row select switches of the row, such that both the row reset switches and the row select switches can be controlled by suitable control signals produced for that row by a row decoder. Examples of these control signals are shown in FIGS. 3 and 4. As shown therein, the pixels of each row receive a common row reset signal Row_r(i) and a common row select signal Row_s(i). The row reset signal for a given row controls the row reset switches of the pixels of that row, and the row select signal for a given row controls the row select switches of the pixels of that row. FIGS. 3 and 4 also illustrate conventional column readout lines, designated as Col_s(m) and Col_s(n). These column readout lines are driven by the pixel elements during column readout.
It is desirable in view of the foregoing to provide for image compression without the aforementioned cost, space and power consumption disadvantages associated with conventional image compression arrangements.
The present invention provides readout control signals that permit the pixels of an image sensor array to be read out in blocks that are compatible with the operation of a desired image compression algorithm. This reduces the amount of memory required by the image compression algorithm, thereby advantageously permitting a more highly integrated image compression system with correspondingly reduced cost, space and power consumption requirements.